1. Field of Invention
The present invention relates to a non-volatile memory (NVM) device. More particularly, the present invention relates to a flash memory device structure and manufacturing method thereof.
2. Description of Related Art
Flash memory is a memory device that allows multiple data writing, reading, and erasing operations. In addition, the stored data will be retained even after power to the device is removed. With these advantages, it has been broadly applied in personal computer and electronic equipment.
A typical flash memory device has a floating gate and a control gate fabricated using doped polysilicon. The control gate is set up above the floating gate with an inter-gate dielectric layer separating the two. Furthermore, a tunneling oxide layer is also setup between the floating gate and an underlying substrate (the so-called stack gate flash memory).
To write data into the flash memory, a bias voltage is applied to the control gate and the source/drain regions so that an electric field is set up to inject electrons into the floating gate. On the other hand, to read data from the flash memory, an operating voltage is applied to the control gate. Since the entrapment of charges inside the floating gate will directly affect the opening or closing of the underlying channel, the opening or closing of the channel can be construed as a data value of “1” or “0”. Finally, to erase data from the flash memory, the relative potential between the substrate and the drain (source) region or the control gate is raised. Hence, tunneling effect can be utilized to transfer electrons from the floating gate to the substrate or drain (source) via the tunneling oxide layer (the so-called substrate erase or drain (source) side erase) or from the floating gate to the control gate via the inter-gate dielectric layer.
FIG. 1 is a schematic cross-sectional view of the stack gate structure of a conventional flash memory (according to U.S. Pat. No. 6,214,668). As shown in FIG. 1, the flash memory comprises of a P-type substrate 100, a deep N-well region 102, a P-well region 104, a stack gate structure 106, a source region 108, a drain region 110, spacers 112, an inter-layer dielectric layer 114, a contact 116 and a conductive line 118. The deep N-well region 102 is embedded within the P-type substrate 100 and the stack gate structure 106 is set up over the P-type substrate 100. The stack gate structure 106 furthermore comprises a tunneling oxide layer 120, a floating gate 122, an inter-gate dielectric layer 124, a control gate 126 and a gate cap layer 128. The source region 108 and the drain region 110 are located within the P-type substrate 100 on each side of the stack gate structure 106. The spacers 112 are attached to the sidewalls of the stack gate structure 106. The P-type well region 104 is within the deep N-well region 102 and extends from the drain region 110 to the area underneath the stack gate structure 106. The inter-layer dielectric layer 114 is above the P-type substrate 100. The contact 116 passes through the inter-layer dielectric layer 114 and the P-type substrate 100 and short-circuits the drain region 110 and the P-type well region 104. The conductive line 118 is positioned over the inter-layer dielectric layer 114 but is electrically connected to the contact 116.
However, as the level of integration of integrated circuits increases and the miniaturization of devices continues, some problems arise. For example, in order to increase the level of integration of a memory device, dimension of each flash memory cell must be reduced. One method of reducing overall memory cell dimension is to shorten the gate length and the separation between data lines. However, reducing the gate length will shorten the channel layer underneath the tunneling oxide layer 120 rendering an electric punch-through between the drain region 110 and the source region 108 more probable. Should such electrical punch-through occur within the device, electrical performance of the memory cell will be seriously compromised. In addition, the photolithographic process used for fabricating the flash memory also has the so-called critical dimension problem, thereby setting a lower limit to the ultimate cell dimension. Furthermore, the drain region 110 and the P-well region 104 are short-circuited together and the P-type well region 104 extends from the drain region 110 into the area underneath the stack gate structure 106. Hence, the P-type well region 104 may not have sufficient thickness in the lateral direction to enclose the drain region (N+ doped). When the memory cell is programmed, the source region receives a voltage of about 6V so that the drain region is at 0V. With this voltage setup, a NPN junction may break down leading to some adverse effect on a nearby flash memory cell. Thus, the ultimate level of integration in a conventional flash memory structure is severely limited.